1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, especially to MOS transistors with gate insulating films of different thickness and a method of manufacturing such MOS transistors.
2. Description of the Background Art
For cost reduction and performance improvement over semiconductor devices, it is essential to scale down the semiconductor devices. For the scale-downs, a gate insulating film of each MOS transistor needs to be as thin in thickness as the other parts of the transistor. The reduction of the thickness of the gate insulating film, however, causes a reduction in the gate breakdown voltage of the MOS transistor.
While the MOS transistor with a thin gate insulating film is suitable as transistors which make for example a logic circuit for performing a logic operation (the breakdown voltage of which is 2-5 V), it is not suitable for circuit portions such as an input circuit which require a relatively high breakdown voltage (5-10 V).
In recent semiconductor integrated circuit devices which comprise on the same substrate circuit portions operating at different driving voltages (e.g., a logic circuit, an input/output circuit, a memory portion), a plurality of kinds of MOS transistors with gate insulating films of different thickness are properly used depending on the circuit portions, whereby the scale-downs of the semiconductor devices are achieved.
For example, a region where a MOS transistor having a 1- to 4-nm-thick gate insulating film and operating at a driving voltage of 0.8 to 1.8 V is located, is referred to as a “thin-film portion”, while a region where a MOS transistor having a 4- to 12-mm-thick gate insulating film and operating at a driving voltage of 1.8 to 5 V is located, is referred to as a “thick-film portion”. And each portion is formed of a proper MOS transistor.
Such a technique of using gate insulating films (especially, gate oxide films) of different thickness is called a dual oxide process and is getting important these days.
Referring now to FIGS. 28 and 29, two kinds of MOS transistors 10 and 20 formed by a conventional dual oxide process will be described hereinbelow.
FIG. 28 shows cross-sectional shapes of the MOS transistors 10 and 20 longitudinally of their gates, and FIG. 29 shows cross-sectional shapes thereof transversely of the gates.
As shown in FIGS. 28 and 29, the MOS transistor 10 is formed with a relatively thick gate oxide film in a thick-film portion AR, and the MOS transistor 20 is formed with a relatively thin gate oxide film in a thin-film portion BR.
The MOS transistors 10 and 20 are located in active regions 3A and 3B, respectively, which are defined by an isolation insulating film 2 formed in the surface of a semiconductor substrate 1. The isolation insulating film 2 is a kind of element isolation insulating films called ST1 (Shallow Trench Isolation).
In the surfaces of the active regions 3A and 3B, well regions 4A and 4B are located, respectively, and channel implant regions 5A and 5B are located in the surfaces of the well regions 4A and 4B, respectively.
On the main surface of the semiconductor substrate 1, gate oxide films GX1 and GX2 of different thickness are located in the active regions 3A and 3B, respectively, and gate electrodes GT1 and GT2 are located on top of the gate oxide films GX1 and GX2, respectively.
Further, an interlayer insulation film 6 is located to cover the gate electrodes GT1 and GT2, on top of which planarized interlayer insulation films 7 and 8 are located.
Corresponding to the MOS transistors 10 and 20, contact portions 9A and 9B are provided, respectively, passing through the interlayer insulation films 6 to 8. As shown in FIG. 29, the contact portions 9A and 9B are electrically connected to source/drain regions SDA and SDB of the MOS transistors 10 and 20, respectively. Further as shown, sidewall oxide films OW1 and GW2 are located on the side faces of the gate electrodes GT1 and G12, respectively. The gate electrodes GT1 and GT2 are also connected respectively to the contact portions 9A and 9B, which is however not shown in FIGS. 28 and 29 for convenience's sake.
As shown in FIGS. 28 and 29, the isolation insulating film 2 which defines the active region 3B in the thin-film portion BR has an excessively removed edge portion on the side of the MOS transistor 20, and thereby a recess is formed in the edge portion of the active region 3B.
Next, a method of manufacturing the MOS transistors 10 and 20 will be described step by step with reference to FIGS. 30 to 34.
In a step of FIG. 30, the isolation insulating film 2 is selectively formed in the surface of the semiconductor substrate 1 to define the active regions 3A and 3B. After formation of a thermal oxide film (not shown), the well regions 4A, 4B and the channel implant regions 5A and 5B are formed by impurity ion implantation, more specifically well formation and channel doping, in the active regions 3A and 3B.
In a step of FIG. 31, the main surfaces of the active regions 3A and 3B are thermally oxidized to form an oxide film OX3 of a third thickness. Here, the “third thickness” is defined as a resultant thickness from subtraction of a second thickness from a first thickness, where the first and second thicknesses are respectively the thicknesses of the gate oxide films GX1 and GX2 to be formed later.
In a step of FIG. 32, a resist pattern RM1 is formed by a photolithographic technique to cover the thick-film portion AR.
Then, the oxide film OX3 in the thin-film portion BR is removed by wet etching for a predetermined period of time. At this time, the edge portion of the isolation insulating film 2 formed of an oxide film is excessively removed and thereby the active region 3B is protruded.
After removal of the resist pattern RM1, in a step of FIG. 33, the oxide film OX3 is increased in thickness to form the gate oxide film GX1 of the first thickness on top of the active region 3A. At this time, the gate oxide film GX2 of the second thickness is formed on top of the active region 3B.
In a step of FIG. 34, a conducting layer CL is formed to cover the gate oxide films GX1 and GX2.
The conducting layer CL is patterned to form the gate electrodes GT1 and GT2. With the gate electrodes GT1 and GT2 as masks, ion implantation is carried out to form the source/drain regions SDA and SDB in the active regions 3A and 3B, respectively.
After the interlayer insulation films 6 to 8 are stacked one above the other over the whole surface, the contact portions 9A and 9B are formed, reaching the source/drain regions SDA and SDB respectively through the interlayer insulation films 6 to 8. This provides the MOS transistors 10 and 20 shown in FIGS. 28 and 29.
In the conventional dual oxide process, as has been described, the oxide film OX3 is once formed and then removed by wet etching to form the thin gate oxide film GX2 in the thin-film portion BR. The edge portion of the isolation insulating film 2 is thus excessively removed and thereby the active region 3B is protruded.
FIG. 35 shows the details of a region X in FIG. 33. As shown in FIG. 35, a depth of an excessively removed portion of the edge portion of the isolation insulating film 2 which faces the active region 3B is 5 nm (50 Å) or less, the depth being defined as a depth between the main surface of the active region 3B and the deepest part of the recess. The horizontal distance between the active region 3B and the isolation insulating film 2 is 0.1 μm or less and the angle of inclination of the protruded portion of the active region 3B ranges from 65° to 90°.
Such an excessively removed portion of the edge portion of the isolation insulating film 2 causes a reduction in threshold voltage due to an inverse narrow-channel effect. Further, the depth of an excessively removed portion varies depending on the time for wet etching of the oxide film OX3 in the thin-film portion BR.
Consequently, the threshold voltage varies depending on the depth of an excessively removed portion of the edge portion of the isolation insulating film 2, which considerably reduces manufacturing yield of the semiconductor device.